Pixel sensor cell with a dual work function gate electrode

ABSTRACT

Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 13/029,670,filed Feb. 17, 2011, which is hereby incorporated by reference herein inits entirety.

BACKGROUND

The invention relates generally to semiconductor device fabrication and,in particular, to pixel sensor cells and methods of fabricating pixelsensor cells, as well as design structures for a pixel sensor cell.

Digital cameras and optical imaging devices, such as web cameras andcell phone cameras, may employ (CMOS) pixel sensor cells to convert avisual image to digital data that may be represented by a picture. Eachpixel sensor cell includes multiple photodiodes each masked by anoptical filter with a different passband representing a range ofwavelengths transmitted with minimal attenuation. Each photodiodeconverts the incident light into charge carriers that are collected in acharge collection well. Periodically, charge is transferred from thecharge collection well to a floating diffusion region of the pixelsensor cell and temporarily stored. During a read out of the pixelsensor cell, a read circuit detects the amount of stored charge andconverts the stored charge into an output voltage from the pixel sensorcell.

Improved pixel sensor cells and fabrication methods for pixel sensorcells, as well as design structures for pixel sensor cells, are needed.

BRIEF SUMMARY

In an embodiment of the invention, a method is provided for fabricatinga pixel sensor cell. The method includes forming a gate dielectric for agate structure of the pixel sensor cell, forming a first section of agate electrode on the gate dielectric, and forming a second section ofthe gate electrode on the gate dielectric. The first and second sectionsof the gate electrode have a juxtaposed relationship to define a layerof the gate electrode. The second section of the gate electrode iscomprised of a conductor. The first section of the gate electrode iscomprised of a metal having a higher work function than the conductorcomprising the second section of the gate electrode so that the gatestructure has an asymmetric threshold voltage.

In an embodiment of the invention, a pixel sensor cell includes aphotosensing element, a floating diffusion region, and a gate structureconfigured to control carrier transfer from the photosensing element tothe floating diffusion region. The gate structure includes a gateelectrode and a gate dielectric. The gate electrode includes a layercomprised of first and second sections that have a juxtaposedrelationship on the gate dielectric. The second section of the gateelectrode is comprised of a conductor, such as doped polysilicon or ametal. The first section of the gate electrode is comprised of a metalhaving a higher work function than the conductor comprising the secondsection of the gate electrode so that the gate structure has anasymmetric threshold voltage.

In another embodiment, a hardware description language (HDL) designstructure is encoded on a machine-readable data storage medium. The HDLdesign structure comprises elements that, when processed in acomputer-aided design system, generates a machine-executablerepresentation of a pixel sensor cell. The HDL design structurecomprises a photosensing element, a floating diffusion region, and agate structure configured to control carrier transfer from thephotosensing element to the floating diffusion region. The gatestructure includes a gate electrode and a gate dielectric. The gateelectrode includes a layer comprised of first and second sections thathave a juxtaposed relationship on the gate dielectric. The secondsection of the gate electrode is comprised of a conductor, such as dopedpolysilicon or a metal. The first section of the gate electrode iscomprised of a metal having a higher work function than the conductorcomprising the second section of the gate electrode so that the gatestructure has an asymmetric threshold voltage. The HDL design structuremay comprise a netlist. The HDL design structure may also reside onstorage medium as a data format used for the exchange of layout data ofintegrated circuits. The HDL design structure may reside in aprogrammable gate array.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments of theinvention and, together with a general description of the inventiongiven above and the detailed description of the embodiments given below,serve to explain the embodiments of the invention.

FIGS. 1-7 are cross-sectional views of a portion of a substrate atsuccessive fabrication stages of a processing method for fabricating apixel sensor cell in accordance with an embodiment of the invention.

FIG. 4A is a top view of the substrate portion at the fabrication stageof FIG. 4.

FIG. 6A is a top view of the substrate portion at the fabrication stageof FIG. 6.

FIG. 8 is a cross-sectional view of a pixel sensor cell in accordancewith an alternative embodiment of the invention.

FIG. 9 is a flow diagram of a design process used in semiconductordesign, manufacture, and/or test.

DETAILED DESCRIPTION

Embodiments of the invention are generally directed to a pixel sensorcell that includes a transfer gate with an asymmetric threshold voltage,V_(t). The asymmetry in the threshold voltage may be produced by using agate structure for the transfer gate that incorporates a high-K gatedielectric and a gate electrode with materials having two differenteffective work functions. For example, the gate electrode may include aplurality of metal sections arranged in a juxtaposed arrangement as anelectrode layer or, alternatively, at least one metal section juxtaposedwith a polysilicon section in an electrode layer. The divergent workfunctions for the different sections of the gate electrode promote theability to modulate the threshold voltage across the gate structure. Thegate electrode section of higher work function exhibits a higherthreshold voltage and is located adjacent to the photosensitive region(e.g., a pinned photodiode) of the pixel sensor cell. The gate electrodesection of lower work function exhibits a lower threshold voltage and isadjacent to the floating diffusion region of the pixel sensor cell. Thelateral modulation of the threshold voltage optimizes the channelpotential with a built-in electric field to sweep electrons toward thefloating diffusion region and to avoid spillback to the photosensitiveregion.

Embodiments of the invention are described herein in terms of a “pixelsensor cell”. It is noted that the term “pixel sensor cell” is used togenerally refer to any type of sensor cell that is capable of convertingincident electromagnetic radiation into an electrical signal. An exampleof a pixel sensor cell according to the invention includes a pixelsensor cell that is capable of detecting optical wavelengths ofelectromagnetic radiation and is commonly referred to as an “imagesensor”. An image sensor fabricated using CMOS technology is commonlyreferred to as a “CMOS image sensor”.

With reference to FIG. 1 and in accordance with an embodiment of theinvention, a semiconductor layer 10 is comprised of a semiconductormaterial that a person having ordinary skill in the art would recognizeas suitable for forming an integrated circuit. For example, thesemiconductor layer 10 may be comprised of a monocrystallinesilicon-containing material, such as bulk single crystal silicon or asilicon-on-insulator (SOI) layer. The semiconductor materialconstituting semiconductor layer 10 may be lightly doped with animpurity to alter its electrical properties. Specifically, thesemiconductor layer 10 may be lightly doped with a concentration of ann-type impurity species (e.g., arsenic) to render it initially lightlydoped n-type (n⁻) semiconductor material or lightly doped with aconcentration of a p-type impurity species (e.g., boron or indium) torender it initially lightly doped p-type (p⁻) semiconductor material.The semiconductor layer 10 may be an epitaxial layer grown on a bulksubstrate of higher doping (e.g., p⁺) and the light-doping state ofsemiconductor layer 10 may result from doping during epitaxial growth.

An isolation structure 15 may be formed in the semiconductor layer 10 bya shallow trench isolation (STI) technique that relies on conventionallithography and dry etching processes to define trenches insemiconductor layer 10, fills the trenches with portions of a dielectricmaterial, and planarizes the dielectric material to the top surface 12of semiconductor layer 10 using a chemical mechanical polishing (CMP)process. The dielectric material contained in isolation structure 15 maybe an oxide, such as densified tetraethylorthosilicate (TEOS) depositedby thermal chemical vapor deposition (CVD) or a high-density plasma(HDP) oxide deposited with plasma assistance. The isolation structure15, which is formed proximate to the invented location of the pixelsensor cell, functions to isolate the cell from adjacent pixel sensorcells of similar construction.

A dielectric layer 14 is formed on a top surface 12 of the semiconductorlayer 10. The dielectric layer 14 will eventually contribute toformation of gate dielectrics for the transfer and reset transistors.The dielectric layer 14 may be comprised of a high dielectric constant(high-k) dielectric material characterized by a relatively highdielectric constant (e.g., permittivity) and may have a layer thicknessranging from 1 nm to 15 nm. As used herein, candidate high-k dielectricsare considered to have a dielectric constant greater than 10 and,preferably, in a range of 10 to 100. Air, which is an accepted referencepoint for values of relative permittivity or dielectric constant, has adielectric constant of approximately unity. Representative high-kdielectric materials for dielectric layer 14 include, but are notlimited to, hafnium-based dielectric materials like hafnium oxide(HfO₂), hafnium silicate (HfSiO), or nitrided hafnium silicate (HfSiON),aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), titanium dioxide(TiO₂), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂), zirconiumsilicon oxide (ZrSiO), yttrium oxide (Y₂O₃), strontium oxide (SrO), orstrontium titanium oxide (SrTiO), mixtures thereof, or layered stacks ofthese and other dielectric materials. These types of high-k dielectricmaterials may be deposited by atomic layer deposition (ALD), CVD, oranother conventional deposition technology. Use of a high-k dielectricin a gate structure of a transistor has been observed to significantlyreduce leakage currents, which reduces power consumption for thetransistor.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage, the dielectriclayer 14 is patterned with a lithography and etching process to formgate dielectrics 16, 18 at the intended locations for the gatestructures of the transfer and reset transistors. To form gatedielectric 16, 18, a resist (not shown) is applied on a top surface ofthe dielectric layer 14 by a spin coating process, pre-baked, exposed toa radiation projected through a photomask, baked after exposure, anddeveloped with a chemical developer to form a mask that includes islandscoinciding spatially with the intended locations of gate dielectrics 16,18. The pattern is transferred from the mask to the dielectric layer 14with a wet etching process or dry etching process, such as areactive-ion etching (RIE) or a plasma etching process. Dielectricmaterial in dielectric layer 14 that is unprotected by the mask islandsis removed by the etching process to define the gate dielectrics 16, 18.The etching process relies on an etchant chemistry that removes thedielectric material of the dielectric layer 14 selective to (i.e., at ahigher etch rate than) the material constituting the semiconductor layer10 and preferably stops on the top surface 12 of the semiconductor layer10. The resist is removed by ashing or solvent stripping and aconventional cleaning process is applied.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage, a layer 20 ofa conductor is formed as a conformal additive layer directly on the topsurface 12 of the semiconductor layer 10 and the gate dielectrics 16,18. The conductor layer 20 may have a layer thickness ranging from 1 nmto 5 nm. The conductor layer 20 may be comprised of a material thatincludes a transition metal. In various embodiments, the transitionmetal may be selected from tungsten (W), tantalum (Ta), titanium nitride(TiN), zirconium nitride (ZrN), hafnium nitride (HfN), vanadium nitride(VN), niobium nitride (NbN), tantalum nitride (TaN), tungsten nitride(WN), titanium aluminum nitride (TiAlN), tantalum carbide (TaC),tantalum magnesium carbide (TaMgC), tantalum carbonitride (TaCN), acombination or an alloy thereof, or analogous materials recognized by aperson having ordinary skill in the art. The metal constitutingconductor layer 20 may be deposited by CVD, ALD, physical vapordeposition (PVD), etc.

With reference to FIGS. 4 and 4A in which like reference numerals referto like features in FIG. 3 and at a subsequent fabrication stage, asection 22 of a gate electrode 40 (FIG. 7) for a transfer gate is formedfrom the conductor layer 20. To that end, a patterned etch mask (notshown) is applied on a top surface of the conductor layer 20. To thatend, a resist (not shown) is applied on a top surface of the conductorlayer 20 by a spin coating process. The resist is pre-baked, exposed toa radiation projected through a photomask, baked after exposure, anddeveloped with a chemical developer to form an etch mask. The etch maskincludes an island of resist at the intended locations of the gateelectrode section 22. In particular, the island of resist used to formthe gate electrode section 22 has a surface area that is smaller thanthe surface area of the top surface 24 of gate dielectric 16.

An anisotropic etching process removes the conductor layer 20 fromsurface areas that are unprotected by the etch mask. The process may bea dry etching process, such as RIE or a plasma etching process, thatrelies on an etchant chemistry that removes the material of theconductor layer 20 selective to (i.e., at a higher etch rate than) thematerials constituting the semiconductor layer 10 and the gatedielectrics 16, 18. The etching process preferably stops on the topsurface 12 of the semiconductor layer 10. The resist is stripped and aconventional cleaning process is applied.

Because of the masking, the gate electrode section 22 for the transfergate is characterized by a width, W₁, which is narrower than the width,W₂, of the gate dielectric 16. The gate electrode section 22 for thetransfer gate is characterized by a length, L, which may be equal to theoriginal length of the gate dielectric 16. The gate electrode section 22directly contacts the top surface 24 of the gate dielectric 16 and has aphysical layer thickness, H₁, that may be approximately equal to thephysical layer thickness of the conductor layer 20.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage, a layer 28 ofa conductor is formed as a conformal additive layer directly on the topsurface 12 of the semiconductor layer 10, the exposed top surface 24 ofgate dielectric 16, and the gate electrode section 22. The conductorlayer 28 may have a layer thickness ranging from 1 nm to 5 nm, and thelayer thickness may be matched to the layer thickness of conductor layer20. The conductor layer 28 may be comprised of the same metals asconductor layer 20, namely W, Ta, TiN, ZrN, HfN, VN, NbN, TaN, WN,TiAlN, TaC, TaMgC, TaCN, a combination or an alloy thereof, or analogousmaterials recognized by a person having ordinary skill in the art, whichmay be deposited by CVD, ALD, PVD, etc. However, the work function ofthe metal selected to comprise conductor layer 28 differs from the workfunction of the metal selected to comprise conductor layer 20. Inparticular, the work function of the metal selected for conductor layer28 may be selected to be smaller than the work function of the metalselected to comprise conductor layer 20.

With reference to FIGS. 6, 6A in which like reference numerals refer tolike features in FIG. 5 and at a subsequent fabrication stage, a section32 of the gate electrode 40 for the transfer gate and a section 34 of agate electrode 42 for a reset gate are formed from the conductor layer28. To that end, a patterned etch mask (not shown) is applied on a topsurface of the conductor layer 28. To that end, a resist (not shown) isapplied on a top surface of the conductor layer 28 by a spin coatingprocess. The resist is pre-baked, exposed to a radiation projectedthrough a photomask, baked after exposure, and developed with a chemicaldeveloper to form an etch mask. The etch mask includes islands of resistat the intended locations of the gate electrode sections 32, 34. Inparticular, the island of resist used to form the gate electrode section32 has a surface area that is smaller than the surface area of the gatedielectric 16 and the island of resist used to form the gate electrodesection 34 has a surface area that is commensurate in size with thesurface area of the gate dielectric 18. The surface area of the islandof resist used to form the gate electrode section 32 is approximatelyequal to the exposed surface area of the top surface 24 of the gatedielectric 16 that is not occupied by gate electrode section 22. Theisland of resist used to form the gate electrode section 34 has asurface area that is commensurate in size with the surface area of thegate dielectric 18.

An anisotropic etching process removes the conductor layer 28 fromsurface areas on the top surface 12 of dielectric layer 10 that areunprotected by the etch mask. The process may be a dry etching process,such as RIE or a plasma etching process, that relies on an etchantchemistry that removes the material of the conductor layer 28 selectiveto (i.e., at a higher etch rate than) the materials constituting thesemiconductor layer 10 and the gate electrode section 22. The etchingprocess preferably stops on the top surface 12 of the semiconductorlayer 10. The resist is stripped and a conventional cleaning process isapplied.

The gate electrode section 32 for gate electrode 40 of the transfer gateis characterized by a width given by the difference between width, W₁,and width, W₂. The gate electrode section 32 is characterized by alength, L, which may be equal to the original length of the gatedielectric 16 and the length of the gate electrode section 22. The gateelectrode section 32 directly contacts the top surface 24 of the gatedielectric 16 and has a juxtaposed relationship with the gate electrodesection 22 to define a layer 30 of the gate electrode 40.

A person having ordinary skill in the art will appreciate that, whilethe gate electrode section 32 is formed after gate electrode section 22in the representative embodiment, the gate electrode section 32 may beformed before gate electrode section 22.

The gate electrode section 34 for gate electrode 42 of the reset gatehas a uniform layer thickness across its length and width, and directlycontacts a top surface of the gate dielectric 18. Because of themasking, the dimensions of the gate electrode section 34 arecommensurate with the dimensions of the gate dielectric 18.

With reference to FIG. 7 in which like reference numerals refer to likefeatures in FIG. 6 and at a subsequent fabrication stage, the gateelectrodes 40, 42 are completed to respectively form a gate structure 60for the transfer gate of a pixel sensor cell 64 and a gate structure 62for the reset gate of the pixel sensor cell 64. Gate electrode sections36, 38 are comprised of a different type of material than the materialsof gate electrode sections 22, 32, 34. In particular, the gate electrodesections 36, 38 are comprised of a material having a lower work functionthan the respective materials comprising any of the gate electrodesections 22, 32, 34. In one embodiment, the gate electrode sections 36,38 are comprised of polysilicon, which is characterized by a lower workfunction than the materials of the gate electrode sections 22, 32, 34.The gate electrode sections 36, 38 may be formed by depositing a blanketlayer of polysilicon by CVD using either silane or disilane as a siliconsource, forming a patterned resist mask (not shown) on the blanketpolysilicon layer, and using an anisotropic etching process to removeportions of the blanket polysilicon layer not masked by the patternedresist mask.

The gate structure 60 of the transfer gate includes the gate dielectric16 and the gate electrode 40. Sidewalls 26, 27 of the gate electrodesections 22, 32, 36 of gate electrode 40 are aligned with the underlyingsidewalls of the gate dielectric 16 to form a layer stack. The gatedielectric 16 is interposed between the gate electrode 40 and the topsurface 12 of the semiconductor layer 10 and, in particular, isinterposed between the gate electrode 40 and a planar channel region 44in the semiconductor layer 10 that is controlled by the transfer gate.The gate structure 60 overlies the channel region 44 and is electricallyconnected with one or more contacts (not shown).

Sidewall spacers 46, 48 are formed on the gate electrodes 40, 42 by aconventional spacer formation process. The sidewall spacers 46, 48 maybe formed by depositing a conformal layer of an electrically insulatingmaterial, such as about ten (10) nanometers to about fifty (50)nanometers of Si₃N₄ deposited by CVD, and anisotropic etching theconformal layer to preferentially remove the electrically insulatingmaterial from horizontal surfaces. The electrical conductivity ofdielectric material in the sidewall spacers 46, 48 is substantially lessthan the electrical conductivity of the conductor in the gate electrodes40, 42. In an alternative embodiment, the sidewall spacers 46, 48 may beomitted.

The pixel sensor cell 64 is then completed by forming a chargecollection well 52, a pinning layer 50 for the charge collection well52, a floating diffusion region 54, and a contact region 56 in thesemiconductor layer 10. The sidewall 26 of gate electrode 40 isproximate or adjacent to the charge collection well 52 and pinning layer50. The gate electrode sections 22, 32 have a juxtaposed arrangement ingate electrode layer 30 contained in a plane that is parallel to the topsurface 12 of the dielectric layer 10. The gate electrode section 32 ofgate electrode 40 is separated from sidewall 26 by the width, W₁, of thegate electrode section 22. The sidewall 27 of gate electrode 40 isseparated from sidewall 26 by the width, W₂, of gate electrode sections22, 32 in the gate electrode layer 30.

The pinning layer 50 is disposed vertically between the chargecollection well 52 and the top surface 12 of the semiconductor layer 10and laterally between the channel region 44 of the gate structure 60 andthe isolation structure 15. The charge collection well 52 is spaced fromthe top surface 12 by the intervening pinning layer 50. The floatingdiffusion region 54 is separated laterally from the charge collectionwell 52 by the channel region 44 of the gate structure 60 and issuitably close to the top surface 12 for establishing electricalconnection with one or more contacts (not shown).

The charge collection well 52 of pixel sensor cell 64 has an oppositeconductivity type to the semiconductor layer 10. The charge collectionwell 52 serves as a source for the transfer gate that includes gatestructure 60. The charge collection well 52 is formed using animplantation mask and an ion implantation process to introduce asuitable impurity species as a dopant into the semiconductor layer 10 ata location adjacent to the gate electrode 40. The implantation mask maybe formed by applying a photoresist layer with a spin coating process,exposing the photoresist to radiation imaged through a photomask, anddeveloping the exposed photoresist to provide a window at the intendedlocation in semiconductor layer 10 for the charge collection well 52.The edge of the window coincides with the edge of the sidewall spacer 46or, if the sidewall spacer 46 is omitted, the window edge coincides withthe sidewall 26 of the gate electrode 40.

A conventional implantation process is used to generate and implantenergetic ions of the impurity species. The charge collection well 52may be formed with multiple implantations at different kinetic energiesthat collectively provide a doped region in the semiconductor materialof semiconductor layer 10 characterized by an appropriate dopantconcentration and dopant depth distribution. The doses and projectedranges of the impurity species are selected to supply a dopantconcentration suitable for the photodiode region, such as a light dopantconcentration. The thickness of the ion implantation mask is selected tostop the energetic ions outside of the window in the photoresist. Theconductivity type of the dopant used to form the photodiode region isopposite to the conductivity type of the dopant used to form thephotodiode pinning layer. In one embodiment, the impurity species is anelement from Group V of the Periodic Table (e.g., phosphorus, arsenic orantimony) effective to act as a dopant to impart an n-type conductivityin the semiconductor material of the semiconductor layer 10.

The pinning layer 50 of pixel sensor cell 64 has the same conductivitytype as the semiconductor layer 10 but a higher dopant concentration andan opposite conductivity type than the charge collection well 52. Thepinning layer 50 may be formed using an ion implantation mask and an ionimplantation process to introduce a suitable impurity species as adopant into the semiconductor layer 10. The same implantation mask usedto form the charge collection well 52 may be used to form the pinninglayer 50 or, alternatively, a new implantation mask may be applied.Energetic ions of the impurity species are generated and implanted usinga conventional implantation process. The ion kinetic energy is selectedsuch that the projected range of the ions is at a relatively shallowdepth beneath the top surface 12 of the semiconductor layer 10 andbetween the charge collection well 52 and the top surface 12. Thethickness of the ion implantation mask is selected to stop the energeticions outside of the window in the photoresist. In one embodiment, theimpurity species is an element in Group III of the Periodic Table (e.g.,boron or indium) effective to act as a dopant to impart a p-typeconductivity in the semiconductor material of the semiconductor layer10. The dose of the impurity species is selected to supply a dopantconcentration suitable for the pinning layer 50, such as a moderatedopant concentration, and higher than the concentration in thesemiconductor layer 10.

The floating diffusion region 54 and a contact region 56 of pixel sensorcell 64 have an opposite conductivity type to the semiconductor layer 10and the same conductivity type as the charge collection well 52. Thefloating diffusion region 54 and contact region 56 are located onopposite sides of the gate electrode 42 for the gate structure 62 andmay be formed using an ion implantation mask and an ion implantationprocess to introduce a suitable impurity species as a dopant into thesemiconductor layer 10. The floating diffusion region 54 serves as adrain for the transfer gate that includes gate structure 60 and as asource for reset gate that includes the gate structure 62. The gatestructure 62 for the reset gate includes the gate dielectric 18 and thegate electrode 42 and overlies another planar channel in thesemiconductor layer 10 laterally between the floating diffusion region54 and the contact region 56.

The floating diffusion region 54 and contact region 56 may beconcurrently formed using an ion implantation mask and an ionimplantation process to introduce a suitable impurity species as adopant into the semiconductor layer 10. To that end, an implantationmask is prepared, as described above for the implantation mask used toform the charge collection well 52. However, the implantation mask haswindows that coincide with the intended locations for the floatingdiffusion region 54 and contact region 56. Energetic ions of theimpurity species are generated and implanted using a conventionalimplantation process. The ion kinetic energy is selected such that theprojected range of the ions is at a relatively shallow depth beneath thetop surface 12 of the semiconductor layer 10. The thickness of the ionimplantation mask is selected to stop the energetic ions outside of thewindow in the photoresist. In one embodiment, the impurity species inthe ions is an element in Group V of the Periodic Table (e.g.,phosphorus, arsenic, or antimony) effective to act as a dopant to impartan n-type conductivity in the semiconductor material of thesemiconductor layer 10. The dose of the impurity species is selected tosupply a dopant concentration suitable for a contacted source and drainof an FET device.

The material constituting the gate electrode sections 36, 38 may bedoped to increase their electrical conductivity by the one of theimplantations used to dope the charge collection well 52, the pinninglayer 50, or the floating diffusion region 54.

One or more high-temperature anneals may be required to electricallyactivate the various implanted impurity species, to alleviateimplantation damage, and to re-distribute the impurity species withinthe doped regions. Alternatively, the doped regions may be formed bydopant diffusion inward from the top surface 12 of the semiconductorlayer 10.

The charge collection well 52 and the nearby region of the semiconductorlayer 10, which is oppositely-doped, collectively constitute aphotosensing element in the representative form of a pinned photodiode58. Electron-hole pairs are generated within a depletion region of thephotodiode 58 when impinged by incident light, which is typicallyfiltered with a color filter and focused onto the photosensing elementby a lens. The number of generated electron-hole pairs is proportionalto the number of photons. Photocarriers of one charge type, eitherelectrons or holes, are accumulated and stored in the charge collectionwell 52. The photodiode 58 of pixel sensor cell 64 is “pinned” becausethe potential in the photodiode 58 is pinned to a constant value whenthe photodiode 58 is fully depleted. It should be understood, however,that the pixel sensor cell 64 may include a photogate, a photoconductor,or another type of photon-to-charge converting device, as a substitutefor the pinned photodiode 58.

When voltage is applied to the gate electrode 40 of gate structure 60,the stored photocarriers are transferred from the charge collection well52 through the channel region 44 to the floating diffusion region 54 ofpixel sensor cell 64. The floating diffusion region 54 may be covered byan opaque light shield (not shown) to block light exposure. The floatingdiffusion region 54 stores the photocarriers as electrical charge asdata until a read circuit detects the amount of stored charge andconverts the charge to a pixel output voltage. The gate structure 62 isused to set the floating diffusion region 54 to a known state beforecharge is transferred from the charge collection well 52 to the floatingdiffusion region 54.

The gate electrode sections 22, 32 of gate electrode 40 provide the gatestructure 60 of transfer gate with an asymmetric threshold voltage inwhich the portion of the gate structure 60 on the source side (i.e., theside nearest to the charge collection well 52 and including gateelectrode section 22) has a higher threshold voltage and the portion ofthe gate structure 60 on the drain side (i.e., the side more distantfrom the charge collection well 52 and including gate electrode section32) has a lower threshold voltage. The threshold voltage asymmetry,which arises from the difference in work function between the metalsused to construct the different gate electrode sections 22, 32, improvesthe efficiency of the gate structure 60 of the transfer gate becausecharge can be transferred from the charge collection well 52 to thefloating diffusion region 54 without spilling back some fraction of thecharge into the charge collection well 52 when the gate electrode 40 isswitched off. The improved efficiency reduces lag and noise for thepixel sensor cell 64 in successive image frames.

In an alternative embodiment of the present invention, a replacementgate process is used that relies on a “dummy” gate of a sacrificialmaterial for forming the implanted regions of the pixel sensor cell 64.In this instance, dummy gates are formed on the surface of semiconductorlayer 10 at the intended location for the gate structure including gatedielectric 16 and gate electrode 40 and at the intended location for thegate structure including gate dielectric 18 and gate electrode 42. Thedummy gates are formed before the implantations creating the chargecollection well 52, pinning layer 50, floating diffusion region 54, andcontact region 56 of pixel sensor cell 64 are executed as describedabove. Following formation of the implanted regions, the dummy gates areremoved with an etching process. The gate electrodes 40, 42 and gatedielectrics 16, 18 are formed, as described above, at the respectiveintended locations formerly occupied by the dummy gates. The finalstructure may have approximately the same appearance as in FIG. 7.

With reference to FIG. 8 in which like reference numerals refer to likefeatures in FIG. 7 and in accordance with an alternative embodiment, agate electrode 40 a of a gate structure 60 a of a pixel sensor cell 64 aincludes a gate electrode section 70 that is formed from conductor layer20 and a gate electrode 42 a of a gate structure 62 a of pixel sensorcell 64 a includes a gate electrode section 72 that is also formed fromconductor layer 20. The deposition and patterning of conductor layer 28(FIGS. 5, 6) is omitted in this alternative embodiment. When theconductor layer 20 is patterned by etching, an island of resist isdisposed in registration with a portion of the gate dielectric layer 16and another island of resist is disposed in registration with gatedielectric layer 18. The former resist island is smaller in surface areathan gate dielectric layer 16 and the latter resist island iscommensurate in surface area with gate dielectric layer 18. Followingetching, the gate electrode section 70 resides on the top surface 24 ofthe gate dielectric layer 16 and the gate electrode section 72 resideson the gate dielectric layer 18.

Next, the gate electrodes 40 a, 42 a are completed by forming gateelectrode sections 76, 78, 80 from a different type of material than thematerial of gate electrode sections 70, 72. In particular, the gateelectrode sections 76, 78, 80 are each comprised of a material having alower work function than the material comprising gate electrode sections70, 72. In one embodiment, the gate electrode sections 76, 78, 80 arecomprised of polysilicon, which is characterized by a lower workfunction than the material of the gate electrode sections 70, 72. Thegate electrode sections 76, 78, 80 may be formed by depositing a blanketlayer of polysilicon by CVD using either silane or disilane as a siliconsource, forming a patterned resist mask (not shown) on the blanketpolysilicon layer, and using an anisotropic etching process to removeportions of the blanket polysilicon layer not masked by the patternedresist mask. The unmasked regions of the patterned resist mask arepositioned laterally relative to the top surface 12 of semiconductorlayer 10 in vertical registration with the gate dielectrics 16, 18.

The remainder of a pixel sensor cell 64 a is fabricated as describedabove in connection with FIG. 7 to produce the final device structure ofFIG. 8 that includes the gate electrodes 40 a, 42 a, the optionalsidewall spacers 46, 48, the charge collection well 52, the pinninglayer 50 for the charge collection well 52, the floating diffusionregion 54, and the contact region 56 in the semiconductor layer 10. Thegate electrode 40 a and the gate dielectric 16 collectively define thegate structure 60 a of the transfer gate for pixel sensor cell 64 a. Thegate electrode 42 a and the gate dielectric 18 collectively define thegate structure 42 a of the reset gate for pixel sensor cell 64 a.

Similar to the gate conductor portion 32 (FIG. 7), the gate electrodesection 80 occupies the space atop the top surface 24 of gate dielectric16 in a juxtaposed relationship with the gate electrode section 70.Collectively, the gate electrode sections 70, 80 define a layer 82 ofthe gate electrode 40 a. The material (e.g., polysilicon) of the gateelectrode section 80 is characterized by a lower work function than thematerial of the gate electrode section 70, which endows the gatestructure 60 a with an asymmetrical threshold voltage. The portion ofthe gate structure 60 a on the source side (i.e., the side nearest tothe charge collection well 52 and that includes the gate electrodesection 70) has a higher threshold voltage than the portion of the gatestructure 60 a on the drain side (i.e., the side more distant from thecharge collection well 52 and including the gate electrode section 80).The threshold voltage asymmetry, which arises from the difference inwork function between the materials used to construct the different gateelectrode sections 70, 80 in layer 82 of the gate electrode 40 a,improves the efficiency of the gate structure 60 a because charge can betransferred from the charge collection well 52 to the floating diffusionregion 54 without spilling back some fraction of the charge into thecharge collection well 52 when the gate electrode 40 a is turned off.The improved efficiency reduces lag and noise for the pixel sensor cell64 a in successive image frames.

FIG. 9 shows a block diagram of an exemplary design flow 100 used forexample, in semiconductor IC logic design, simulation, test, layout, andmanufacture. Design flow 100 includes processes, machines and/ormechanisms for processing design structures or devices to generatelogically or otherwise functionally equivalent representations of thedesign structures and/or devices described above and shown in FIGS. 7and 8. The design structures processed and/or generated by design flow100 may be encoded on machine-readable transmission or storage media toinclude data and/or instructions that when executed or otherwiseprocessed on a data processing system generate a logically,structurally, mechanically, or otherwise functionally equivalentrepresentation of hardware components, circuits, devices, or systems.Machines include, but are not limited to, any machine used in an ICdesign process, such as designing, manufacturing, or simulating acircuit, component, device, or system. For example, machines mayinclude: lithography machines, machines and/or equipment for generatingmasks (e.g., e-beam writers), computers or equipment for simulatingdesign structures, any apparatus used in the manufacturing or testprocess, or any machines for programming functionally equivalentrepresentations of the design structures into any medium (e.g., amachine for programming a programmable gate array).

Design flow 100 may vary depending on the type of representation beingdesigned. For example, a design flow 100 for building an applicationspecific IC (ASIC) may differ from a design flow 100 for designing astandard component or from a design flow 100 for instantiating thedesign into a programmable array, for example a programmable gate array(PGA) or a field programmable gate array (FPGA) offered by Altera® Inc.or Xilinx® Inc.

FIG. 9 illustrates multiple such design structures including an inputdesign structure 102 that is preferably processed by a design process104. Design structure 102 may be a logical simulation design structuregenerated and processed by design process 104 to produce a logicallyequivalent functional representation of a hardware device. Designstructure 102 may also or alternatively comprise data and/or programinstructions that when processed by design process 104, generate afunctional representation of the physical structure of a hardwaredevice. Whether representing functional and/or structural designfeatures, design structure 102 may be generated using electroniccomputer-aided design (ECAD) such as implemented by a coredeveloper/designer. When encoded on a machine-readable datatransmission, gate array, or storage medium, design structure 102 may beaccessed and processed by one or more hardware and/or software moduleswithin design process 104 to simulate or otherwise functionallyrepresent an electronic component, circuit, electronic or logic module,apparatus, device, or system such as those shown in FIGS. 7 and 8. Assuch, design structure 102 may comprise files or other data structuresincluding human and/or machine-readable source code, compiledstructures, and computer-executable code structures that when processedby a design or simulation data processing system, functionally simulateor otherwise represent circuits or other levels of hardware logicdesign. Such data structures may include hardware-description language(HDL) design entities or other data structures conforming to and/orcompatible with lower-level HDL design languages such as Verilog andVHDL, and/or higher level design languages such as C or C++.

Design process 104 preferably employs and incorporates hardware and/orsoftware modules for synthesizing, translating, or otherwise processinga design/simulation functional equivalent of the components, circuits,devices, or logic structures shown in FIGS. 7 and 8 to generate aNetlist 106 which may contain design structures such as design structure102. Netlist 106 may comprise, for example, compiled or otherwiseprocessed data structures representing a list of wires, discretecomponents, logic gates, control circuits, I/O devices, models, etc.that describes the connections to other elements and circuits in anintegrated circuit design. Netlist 106 may be synthesized using aniterative process in which netlist 106 is resynthesized one or moretimes depending on design specifications and parameters for the device.As with other design structure types described herein, netlist 106 maybe recorded on a machine-readable data storage medium or programmed intoa programmable gate array. The medium may be a non-volatile storagemedium such as a magnetic or optical disk drive, a programmable gatearray, a compact flash, or other flash memory. Additionally, or in thealternative, the medium may be a system or cache memory, buffer space,or electrically or optically conductive devices and materials on whichdata packets may be transmitted and intermediately stored via theInternet, or other networking suitable means.

Design process 104 may include hardware and software modules forprocessing a variety of input data structure types including Netlist106. Such data structure types may reside, for example, within libraryelements 108 and include a set of commonly used elements, circuits, anddevices, including models, layouts, and symbolic representations, for agiven manufacturing technology (e.g., different technology nodes, 32 nm,45 nm, 90 nm, etc.). The data structure types may further include designspecifications 110, characterization data 112, verification data 114,design rules 116, and test data files 118 which may include input testpatterns, output test results, and other testing information. Designprocess 104 may further include, for example, standard mechanical designprocesses such as stress analysis, thermal analysis, mechanical eventsimulation, process simulation for operations such as casting, molding,and die press forming, etc. One of ordinary skill in the art ofmechanical design can appreciate the extent of possible mechanicaldesign tools and applications used in design process 104 withoutdeviating from the scope and spirit of the invention. Design process 104may also include modules for performing standard circuit designprocesses such as timing analysis, verification, design rule checking,place and route operations, etc.

Design process 104 employs and incorporates logic and physical designtools such as HDL compilers and simulation model build tools to processdesign structure 102 together with some or all of the depictedsupporting data structures along with any additional mechanical designor data (if applicable), to generate a second design structure 120.Design structure 120 resides on a storage medium or programmable gatearray in a data format used for the exchange of data of mechanicaldevices and structures (e.g. information stored in an IGES, DXF,Parasolid XT, JT, DRG, or any other suitable format for storing orrendering such mechanical design structures). Similar to designstructure 102, design structure 120 preferably comprises one or morefiles, data structures, or other computer-encoded data or instructionsthat reside on transmission or data storage media and that whenprocessed by an ECAD system generate a logically or otherwisefunctionally equivalent form of one or more of the embodiments of theinvention shown in FIGS. 7 and 8. In one embodiment, design structure120 may comprise a compiled, executable HDL simulation model thatfunctionally simulates the devices shown in FIGS. 7 and 8.

Design structure 120 may also employ a data format used for the exchangeof layout data of integrated circuits and/or symbolic data format (e.g.information stored in a GDSII (GDS2), GL1, OASIS, map files, or anyother suitable format for storing such design data structures). Designstructure 120 may comprise information such as, for example, symbolicdata, map files, test data files, design content files, manufacturingdata, layout parameters, wires, levels of metal, vias, shapes, data forrouting through the manufacturing line, and any other data required by amanufacturer or other designer/developer to produce a device orstructure as described above and shown in FIGS. 7 and 8. Designstructure 120 may then proceed to a stage 122 where, for example, designstructure 120: proceeds to tape-out, is released to manufacturing, isreleased to a mask house, is sent to another design house, is sent backto the customer, etc.

It will be understood that when an element is described as being“connected” or “coupled” to or with another element, it can be directlyconnected or coupled to the other element or, instead, one or moreintervening elements may be present. In contrast, when an element isdescribed as being “directly connected” or “directly coupled” to anotherelement, there are no intervening elements present. When an element isdescribed as being “indirectly connected” or “indirectly coupled” toanother element, there is at least one intervening element present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. A method for fabricating a pixel sensor cell, themethod comprising: forming a photosensing element beneath a top surfaceof a semiconductor layer; forming a gate dielectric for a first gatestructure on the top surface of the semiconductor layer; forming a firstsection of a gate electrode for the first gate structure on the gatedielectric and adjacent to the photosensing element; and forming asecond section of the gate electrode for the first gate structure on thegate dielectric and in a juxtaposed relationship with the first sectionof the gate electrode as a first layer of the gate electrode, whereinthe first section of the gate electrode is formed with a lateralposition in the first layer between the photosensing element and thesecond section of the gate electrode, the second section of the gateelectrode is comprised of a conductor, and the first section of the gateelectrode is comprised of a first metal having a higher work functionthan the conductor comprising the second section of the gate electrodeso that the first gate structure has an asymmetric threshold voltage. 2.The method of claim 1 further comprising: forming a floating diffusionregion in the semiconductor layer.
 3. The method of claim 2 whereinforming the photosensing element further comprises: forming a chargecollection region of a pinned photodiode in the semiconductor layer andlocated beneath the top surface of the semiconductor layer, wherein thefirst gate structure is configured to control charge transfer from thecharge collection region to the floating diffusion region.
 4. The methodof claim 1 wherein forming the first section of the gate electrode onthe gate dielectric comprises: depositing a first conformal layercomprised of the first metal on the gate dielectric and the top surfaceof the semiconductor layer; and patterning the first conformal layer toform the first section of the gate electrode.
 5. The method of claim 4wherein the conductor is a second metal, and forming the second sectionof the gate electrode on the gate dielectric and in the juxtaposedrelationship with the first section of the gate electrode as the firstlayer of the gate electrode comprises: depositing a second conformallayer comprised of the second metal on the gate dielectric, the topsurface of the semiconductor layer, and the first section of the gateelectrode; and patterning the second conformal layer to form the secondsection of the gate electrode.
 6. The method of claim 5 whereinpatterning the second conformal layer to form the second section of thegate electrode comprises: forming a patterned etch mask on a top surfaceof the second conformal layer and including an island at an intendedlocation of the second section of the gate electrode; and etching thesecond conformal layer to remove portions of the second conformal layerthat are unprotected by the island of the patterned etch mask.
 7. Themethod of claim 5 further comprising: depositing a third conformal layercomprised of polysilicon on the top surface of the semiconductor layer,the first section of the gate electrode, and the second section of thegate electrode; and patterning the conformal polysilicon layer to form asecond layer of the gate electrode that is separated by the first layerof the gate electrode from the gate dielectric.
 8. The method of claim 4wherein the conductor is comprised of polysilicon, and forming thesecond section of the gate electrode on the gate dielectric and in thejuxtaposed relationship with the first section of the gate electrode asthe first layer of the gate electrode comprises: depositing a secondconformal layer comprised of polysilicon on the top surface of thesemiconductor layer and the first section of the gate electrode; andpatterning the conformal polysilicon layer to form the second section ofthe first layer of the gate electrode and a second layer of the gateelectrode that is separated by the first layer of the gate electrodefrom the gate dielectric.
 9. The method of claim 4 wherein patterningthe first conformal layer to form the first section of the gateelectrode comprises: forming a patterned etch mask on a top surface ofthe first conformal layer and including an island at an intendedlocation of the first section of the gate electrode; and etching thefirst conformal layer to remove portions of the first conformal layerthat are unprotected by the island of the patterned etch mask.
 10. Themethod of claim 1 wherein the first section of the gate electrode andthe second section of the gate electrode are each dimensionally smallerthan the gate dielectric.
 11. The method of claim 1 wherein the firstsection of the gate electrode is formed on the gate dielectric beforethe second section of the gate electrode is formed on the gatedielectric.
 12. The method of claim 1 wherein the first metal is atransition metal, the conductor comprises a transition metal, the gateelectrode includes a second layer comprised of polysilicon, and thefirst layer of the gate electrode is positioned between the second layerof the gate electrode and the gate dielectric.
 13. The method of claim 1wherein the first metal is a transition metal, the conductor comprisespolysilicon, the gate electrode includes a second layer comprised ofpolysilicon, and the first layer of the gate electrode is positionedbetween the second layer of the gate electrode and the gate dielectric.14. The method of claim 1 wherein the gate dielectric is comprised of adielectric material having a dielectric constant in a range from 10 to100.
 15. The method of claim 1 further comprising: before forming thegate dielectric, forming a dummy gate on the top surface of thesemiconductor layer at an intended location for the gate dielectric; andafter the dummy gate is formed, implanting the semiconductor layer toform a floating diffusion region on one side of the dummy gate.
 16. Themethod of claim 15 wherein the photosensing element is a pinned diode,and forming the photosensing element in the semiconductor layer furthercomprises: after the dummy gate is formed, implanting the semiconductorlayer to form a charge collection region of the pinned photodiode in thesemiconductor layer on an opposite side of the dummy gate from thefloating diffusion region.
 17. The method of claim 16 furthercomprising: after the floating diffusion region and the chargecollection region are formed, removing the dummy gate with an etchingprocess.
 18. The method of claim 1 further comprising: forming a secondgate structure on the top surface of the semiconductor layer.
 19. Themethod of claim 18 further comprising: implanting the semiconductorlayer to form a floating diffusion region between the first gatestructure and the second gate structure, wherein the photosensingelement is separated from the floating diffusion region by a channel inthe semiconductor layer beneath the first gate structure.